// interactive labs
Labs
25 interactive exercises across 5 domains. Each lab pairs a live simulator with a step-by-step tutorial — no install required.
Circuit Simulator
Browser-based SPICE-style simulator (Falstad embed + MNA solver). Build and probe circuits in real time.
Kirchhoff's Laws
KVL: voltages around any closed loop sum to zero. KCL: currents into any node sum to zero. This series-parallel circuit demonstrates both.
beginnerOhm's Law
Explore V = IR. Adjust voltage or resistance and watch current change in real time.
beginnerVoltage Divider
Two resistors divide an input voltage proportionally. The output voltage depends on the ratio of the resistors.
PCB Design
Interactive PCB layer stackups, impedance calculators, trace routing, DRC, and Gerber viewing.
Design Rule Checking (DRC)
Click the violation markers on the PCB layout to learn what each DRC rule catches, why it matters, and how to fix it.
beginnerPCB Layer Stackups
Explore the cross-section of a PCB. Learn what each layer does and how 2, 4, 6, and 8-layer stackups differ.
beginnerTrace Routing Best Practices
Interactive examples showing 45° routing, differential pair matching, and return path management — the three most impactful PCB layout skills.
beginnerPCB Via Types
Compare through-hole, blind, buried, and microvia cross-sections. Understand which layers each type connects and when to use them.
intermediateControlled Impedance
Use the impedance calculator to design 50 Ω microstrip and stripline traces. Understand how trace geometry and dielectric constant affect characteristic impedance.
Digital Electronics
WaveDrom timing diagrams, truth table generator, CircuitVerse logic simulation, and Yosys/DigitalJS Verilog synthesis.
Logic Gates & Boolean Algebra
Explore logic gates using interactive truth tables. Understand AND, OR, NOT, XOR, NAND, NOR, and XNOR with SOP forms.
beginnerDigital Timing Diagrams
Read and interpret WaveDrom timing diagrams. Understand clock edges, setup/hold times, and signal relationships.
intermediateTruth Tables & Karnaugh Maps
Use the truth table generator to build and simplify Boolean functions. Explore multi-variable expressions and Sum of Products minimisation.
advancedVerilog HDL Introduction
Write synthesisable Verilog and see the gate-level netlist generated by Yosys. Explore a 4-bit adder and modify it to understand synthesis.
Semiconductor Physics
PN junction physics, MOSFET characteristics, band diagrams with Poisson solver, and carrier drift/diffusion animation.
Carrier Transport & Mobility
Animate electron and hole motion under electric fields. See drift velocity, diffusion, the Einstein relation, and how doping and temperature affect mobility.
intermediateMOSFET Operation
Visualise the MOSFET cross-section and I-V characteristics. Explore cutoff, linear (triode), and saturation regions interactively.
intermediatePN Junction Physics
Explore the abrupt PN junction — built-in potential, depletion region, electric field, and the Shockley I-V relationship.
advancedSemiconductor Band Diagrams
Visualise energy band diagrams for PN junctions, MOS capacitors, and MOSFET channels under applied bias using the Poisson equation.
Power Systems
Newton-Raphson & Gauss-Seidel power flow, per-unit converter, IEEE 14-bus validation, and fault analysis.
Per-Unit System
Master the per-unit (pu) system used throughout power engineering. Convert voltages, currents, impedances, and power between physical SI units and per-unit values on a chosen base.
beginnerNewton-Raphson Power Flow
Run a Newton-Raphson power flow on a simple 3-bus network. Observe how voltage magnitudes and angles change as load increases, and understand convergence behaviour.
intermediateGauss-Seidel vs Newton-Raphson
Compare Gauss-Seidel and Newton-Raphson power flow solvers side-by-side. Understand why NR's quadratic convergence makes it the industry standard despite requiring Jacobian computation at each step.
intermediateHarmonic Analysis & G5/5 Compliance
Synthesise a distorted waveform from individual harmonic components, run an FFT, and check the spectrum against ENA EREC G5/5 voltage planning limits — the standard a UK harmonic distortion study has to demonstrate compliance with.
intermediateN-1 Contingency Screening
Single-element outage screening on the IEEE 14-bus test system. Trip a line or transformer and re-solve the power flow — find the post-contingency overloads and voltage violations that would drive remedial actions in a real connection study.
intermediateIEEE 14-Bus System Analysis
Analyse the standard IEEE 14-bus test case — 5 generators, 11 loads, 17 lines, and 3 off-nominal transformers. This benchmark is used worldwide to validate power flow software. Compare your results against the published MATPOWER reference solution.
advancedShort-Circuit Fault Analysis
Calculate fault currents for the four main fault types — 3-phase, line-to-ground, line-to-line, and double line-to-ground — using the Z-bus / symmetrical-component method. Vary the fault impedance and Z₀/Z₁ ratio and watch the fault duty change.
advancedProtection Coordination (IEC Inverse-Time)
Plot two IEC 60255 inverse-time overcurrent relays on the same time-current diagram, slide the fault current cursor, and watch the grading margin go green or red. The minimum workflow for any feeder protection setting calculation.
advancedTransient Stability — Swing Equation
Single-machine-infinite-bus (SMIB) transient stability with a 3-phase line fault. Slide the inertia, mechanical power, and clearing time and watch the rotor angle trajectory either return to a new equilibrium or run away. The equal-area criterion visualised on the P-δ curve gives the intuition.