advanced Digital Electronics

Verilog HDL Introduction

Write synthesisable Verilog and see the gate-level netlist generated by Yosys. Explore a 4-bit adder and modify it to understand synthesis.

The Verilog playground synthesises your code using Yosys WASM (~40 MB) and renders a live gate-level simulation. Click the button below to load it.

Verilog source

The playground loads the pre-written 4-bit ripple-carry adder. Click 'Load Verilog Playground' to download Yosys WASM (~40 MB) and synthesise the design.

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Yosys is an open-source synthesis tool. It converts RTL (register-transfer level) Verilog into a gate-level netlist.
After synthesis, DigitalJS renders an interactive simulation. Toggle the input bits and observe how the output sum and carry change in real time.

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The simulation shows actual gates (AND, OR, XOR, FA cells). You can see how Verilog's '+' operator maps to real hardware.
Modify the code: change 'output [3:0] sum' to 'output [4:0] sum' (5-bit output) and update the assign to 'assign sum = a + b + cin'. Re-synthesise. The carry is now embedded in sum[4].

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RTL Verilog uses arithmetic on bit-vectors. The synthesis tool handles the carry chain automatically.
Try a simple multiplexer: replace the adder with 'module mux2(input sel, input a, input b, output y); assign y = sel ? b : a; endmodule'. Notice Yosys synthesises a single MUX gate.

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The ternary operator in Verilog maps directly to a multiplexer in hardware.
Write a D flip-flop: 'module dff(input clk, input d, output reg q); always @(posedge clk) q <= d; endmodule'. Synthesis will produce a DFF cell — the fundamental building block of sequential logic.

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Sequential logic (flip-flops, registers) uses 'always @(posedge clk)' blocks. Combinational logic uses 'assign' or 'always @(*)'.