beginner Digital Electronics

Digital Timing Diagrams

Read and interpret WaveDrom timing diagrams. Understand clock edges, setup/hold times, and signal relationships.

D Flip-Flop timing

A timing diagram shows signal states over time. The horizontal axis is time; each vertical division is one clock period. 'P' in WaveDrom means a periodic clock (high/low squares).

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CLK is the master clock. All other signals are measured relative to its rising (↑) and falling (↓) edges.
D is the data input to a flip-flop. 'x' means don't-care / unknown. '1' and '0' are logic levels. Observe how D transitions between these states.

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In synchronous digital design, D must be stable for a setup time (tsu) before and a hold time (th) after the clock edge.
Q is the output. Notice that Q only changes after the rising clock edge — the flip-flop samples D at that instant and holds the value until the next edge.

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This is the core concept of synchronous logic: outputs change only on clock edges, preventing glitches from propagating.
The 'Setup' row marks the setup window — D must be stable for this duration before the clock edge. Violating setup time causes a metastability failure.

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Metastability means the flip-flop output is neither 0 nor 1 and can oscillate unpredictably until it resolves.
The 'Hold' row marks the hold time after the clock edge. D must remain stable for this window as well. Hold violations occur in very fast paths (e.g. zero-delay lines).

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Setup time limits the maximum clock frequency; hold time is fixed by the circuit and cannot be fixed by slowing the clock.